Semiconductor devices are being developed to be small in size, multi-functional, and have low power consumption. Accordingly, small and lightweight semiconductor packages are necessary to sufficiently implement desired characteristics into semiconductor devices.
It is often difficult to apply semiconductor device micro-circuit fabrication technology to each product of a fabrication process. Complicated circuits can cause extension of the development period, enormous equipment investment, and an increase in process cost.
A unit cell of static random access memory (SRAM) generally includes six transistors (6T). Specifically, a unit cell of SRAM often includes four n-channel metal oxide semiconductor (NMOS) transistors and two p-channel metal oxide semiconductor (PMOS) transistors.
The implant processes typically required in fabricating SRAM include an implant for forming a well and a channel, an implant for forming a pocket and an lightly-doped drain (LDD), and an implant for forming a source and a drain. Since these processes must be performed for both NMOS and PMOS transistors, six implant processes are required.
Each implant process generally includes a photo process for opening an area in which an implant is to be performed, an ion implantation process for implanting dopants, an ashing process for removing a photoresist, and a cleaning process for removing a polymer that might remain after the ashing process with a cleaning liquid.
Accordingly, to fabricate the SRAM including six transistors, the total number of implant processes required can be 18 or more.
FIG. 1 is a circuit diagram of a related art unit cell of SRAM, and FIG. 2 is a layout of the related art unit cell of SRAM.
Referring to FIGS. 1 and 2, the related art unit cell of SRAM 10 includes four NMOS transistors (T1, T3, T5, T6) and two PMOS transistors (T2, T4) to give six total transistors.
The related art unit cell of SRAM 10 includes: first and sixth transistors T1 and T6, each having a gate connected to a word line WL and a drain connected to a bit line BL and sub-bit line/BL, respectively; second and fourth transistors T2 and T4 having sources to which a power source voltage Vdd is applied; and driving transistors T3 and T5 having a complimentary metal oxide semiconductor (CMOS) structure in which the third transistor T3 is connected in series with the second transistor T2 and have their gates connected to each other, and the fifth transistor T5 is connected in series to the fourth transistor T4 and have their gates connected to each other.
Referring to FIG. 2, an NMOS active area 101b having NMOS transistors is formed on a semiconductor substrate. Also, a PMOS active area 101a having PMOS transistors is formed on the semiconductor substrate. The NMOS and PMOS active areas 101b and 101a are isolated from each other by an isolation layer.
In the NMOS active area 101b, p-type impurities are implanted to form p-wells for the NMOS transistors T1, T3, T5, and T6. In the PMOS active area 101a, n-type impurities are implanted to form n-wells for the PMOS transistors T2 and T4.
FIGS. 3A and 3B are views illustrating an implant process for forming an active area of the related art SRAM.
The related art unit cell of the 6T SRAM undergoes several implant processes to form NMOS and PMOS transistors. The PMOS implant must be performed by covering the NMOS transistors with a photoresist 123 to expose only a PMOS area, and the NMOS implant must be performed by covering the PMOS transistors with a photoresist 121 and to expose only an NMOS area.
In each of the implant processes for the PMOS and NMOS transistors, a well implant, a pocket implant, an LDD implant, and a source/drain implant must be performed, as well as possibly other implant processes. An NMOS area must be covered with a photoresist in the PMOS implant, and a PMOS area must be covered with a photoresist in the NMOS implant. Accordingly, many photo processes must be performed, thereby increasing fabrication time and reducing yield rate.
Thus, there exists a need in the art for an improved semiconductor device and fabrication method thereof.